Field of the Invention
The present invention relates to a memory control device that controls a semiconductor memory, a memory control method, an information device equipped with this memory control device, and a storage medium storing a program that make a computer execute the memory control method.
Description of the Related Art
Improvement in processing speed of a CPU and an LSI for peripheral circuitry requires improvement in data transfer rate of a semiconductor memory in recent years. One of various semiconductor memories is an SDRAM that is a synchronous semiconductor memory. An SDRAM is controlled so as to input and output data in synchronizing with a system clock of an LSI. Control signals, such as RAS, CAS, WE, are inputted into the SDRAM in synchronizing with a rising edge of a system clock CLK. The SDRAM receives a control instruction (command) that is determined by a combination of High level of Low level of these input signals. Moreover, an address and data are also inputted into the SDRAM in synchronizing with the rising edge of the CLK. By achieving such a synchronous semiconductor memory, the data input-and-output transfer rate to a memory improves substantially.
However, a problem that setup times and hold times of various input signals become short occurs to synchronization with the CLK as the data transfer rate of a semiconductor memory improves. In order to achieve a required setup time and hold time in a synchronous semiconductor memory, it is necessary that an initial circuit for inputting an address and data is always in an activated state irrespective of a control instruction. Accordingly, there is a known technique about a semiconductor memory that employs a data strobe signal (DQS) in order to achieve high-speed data transmission. As semiconductor memory that employs the data strobe signal, there are a DDR2 SDRAM, a DDR3 SDRAM, etc., for example.
Incidentally, various types of information devices including a multifunctional peripheral device (MFP) have a problem of increasing power consumption of an LSI and a semiconductor memory inside a device, and are required to reduce power consumption. There is a method of reducing power consumption by locally shifting LSI etc. to a power saving mode (sleep mode) or by shutting off the power supplied to the LSI etc. However, since the data stored in a volatile memory disappears by shutting off the power, it is necessary to save the data stored in a volatile memory to a nonvolatile memory before shutting off the power. Moreover, since the saved data is required to be returned at the next power-on timing, a new problem that start-up time becomes long because data transition takes time occurs.
There is a proposed technique that employs a nonvolatile memory, such as a magnetic reluctance memory (referred to as an “MRAM”, hereafter), as substitution of a volatile memory, such as a DDR3 SDRAM (for example, see Japanese Laid-Open Patent Publication (Kokai) No. 2013-4043 (JP 2013-4043A)). Since an MRAM is able to hold data with magnetism even when the device power shuts off, and allows a high-speed access, it is unnecessary to save the above-mentioned data before shutting off the device power. Moreover, an information device using an MRAM stores a boot program into the MRAM at the first power-on, and executes the boot program read from the MRAM when the power turns on again after shutting off the power. This allows high-speed start-up.
Incidentally, an MRAM is compatible with a DDR3 SDRAM that is a volatile memory. Accordingly, in an information device provided with a plurality of memory slots so that a plurality of memory devices can be implemented, since a user is able to add and exchange memory devices, a DDR3 SDRAM and an MRAM may be intermingled within an information device. In this case, since there is a possibility that the boot program, which should be stored in an MRAM, is stored in a DDR3 SDRAM, the performance of the MRAM cannot be utilized effectively.